As semiconductor chip performance increases, the chip design becomes increasingly complex. The traditional register transfer level (RTL) design methodology is time-consuming for the modern system-on-chip (SoC) design which needs a high integration of software and hardware. It may be too late to revise design if problems are detected in the RTL stage. Therefore, the electronic system level (ESL) design methodology is adopted to facilitate modern system design.
Power consumption has been an important issue in chip design. For the ESL model, power estimation is required for system-level design and technology exploration because an ESL model contains power states and associated power consumption number for each intellectual property (IP) in the ESL model.